Accessing data stored in a command/address register device

ABSTRACT

A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.14/560,976, which is a continuation of U.S. patent application Ser. No.13/995,477 filed Aug. 21, 2014, which is a national phase application ofInternational Patent Application No. PCT/US2011/066891 filed Dec. 22,2011. These applications are incorporated herein by reference in theirentireties.

FIELD

Embodiments of the invention are generally related to memory devices,and more particularly to accessing data stored in a register device on amemory address or command bus.

COPYRIGHT NOTICE/PERMISSION

Portions of the disclosure of this patent document may contain materialthat is subject to copyright protection. The copyright owner has noobjection to the reproduction by anyone of the patent document or thepatent disclosure as it appears in the Patent and Trademark Officepatent file or records, but otherwise reserves all copyright rightswhatsoever. The copyright notice applies to all data as described below,and in the accompanying drawings hereto, as well as to any softwaredescribed below: Copyright© 2011, Intel Corporation, All RightsReserved.

BACKGROUND

Certain memory subsystems include register devices connected to theaddress or command bus of the memory subsystem to store values relatedto a command or a configuration within the memory subsystem.Traditionally there is no good way to access such data. Thus, datastored in the register for purposes of configuration (e.g., data storedin a Mode Register) or data stored for debug or error detection purposes(e.g., data stored in a C/A register device) or other data in anothersuch register is not easily accessible.

One option to access the data is to include a connection to the data busof the memory subsystem. Such an option is very expensive in terms ofhardware (extra pins) and routing of traces. Another option is to putthe device in a special state (e.g., a management mode) to temporarilyallow repurposing of the existing buses or other connections. Such anoption results in a slow connection, and does not allow continuedoperation of the device, and may still require additional hardware.Another option is to provide an out-of-band serial interface on theregister device, which also adds hardware and routing costs. Thus, thereare currently no traditional mechanisms that allow access to the datastored in registers of the memory subsystem with standard commands withminimal hardware requirements.

Memory subsystems that support newer standards of DDR (dual data rate)memory add an additional circumstance of providing a register and logicfor performing parity error checking at the register device instead ofat the memory device. For example, DDR4 (standard still in developmentas of the filing of this application) will allow command/address (C/A)parity error checking off the DRAM (dynamic random access memory)device. However, without a mechanism to read a parity error, the commandwill still be send to the DRAM for execution, which would result inhanging the computing device (for example, a “blue screen” condition).

BRIEF DESCRIPTION OF THE DRAWINGS

The following description includes discussion of figures having,illustrations given by way of example of implementations of embodimentsof the invention. The drawings should be understood by way of example,and not by way of limitation. As used herein, references to one or more“embodiments” are to be understood as describing a particular feature,structure, or characteristic included in at least one implementation ofthe invention. Thus, phrases such as “in one embodiment” or “in analternate embodiment” appearing herein describe various embodiments andimplementations of the invention, and do not necessarily all refer tothe same embodiment. However, they are also not necessarily mutuallyexclusive.

FIG. 1 is a block diagram of an embodiment of a system having a memorysubsystem with a register accessible via an address or command bus butnot a data bus.

FIG. 2 is a block diagram of an embodiment of a system having a memorysubsystem with a register between a memory controller and a DRAM device.

FIG. 3 is a block diagram of an embodiment of a system having a memorysubsystem with a register accessible via an address or command bus butnot a data bus, and a memory device accessible via both the address orcommand bus and data bus.

FIG. 4 is a block diagram of an embodiment of a system having a memorysubsystem with a register device between a memory controller and a DRAMdevice, where the register device performs parity checking.

FIG. 5 is a flow diagram of an embodiment of a process for accessingdata from a register accessible via an address or command bus but not adata bus.

FIG. 6 is a block diagram of an embodiment of a computing system inwhich a register of the memory subsystem is accessed indirectly by ahost processor.

FIG. 7 is a block diagram of an embodiment of a mobile device in which aregister of the memory subsystem is accessed indirectly by a hostprocessor.

Descriptions of certain details and implementations follow, including adescription of the figures, which may depict some or all of theembodiments described below, as well as discussing other potentialembodiments or implementations of the inventive concepts presentedherein. An overview of embodiments of the invention is provided below,followed by a more detailed description with reference to the drawings.

DETAILED DESCRIPTION

As described herein, a register in a memory subsystem is connected to anaddress bus. It will be understood that reference to an address buscould refer to a bus that carries only addresses, or to a bus thatcarries addresses and commands. Many address buses are both address orcommand buses in that both addresses, commands, or combinations ofaddresses and commands are sent over the buses. Reference herein to an“address bus” will be understood to refer to an address or command bus.Thus, a register is accessible via an address or command bus, but not adata bus. The data can be read by transferring data across the addressbus from the register to a device connected to the data bus, from whichthe data is read over the data bus even though the register is notconnected to the data bus. The register resides in a register deviceconnected via the address bus to a memory device that is connected toboth the address bus and the data bus. A host processor triggers theregister device to transfer information over the address bus to aregister on the memory device. The host processor then reads theinformation from the register of the memory device. With such a readmechanism, an “indirect” read of the register is possible.

The read mechanism works with any register device coupled to the addressbus, such as a Mode Register or a parity error checking register device.A specific memory configuration is thus accessible during normal runtimeexecution of the host operating system. Additionally, it is possible toaccess data regarding a specific command or address that resulted in aparity error, which can prevent access and fault of the host system. Itis thus possible through the described read mechanism to perform errorrecovery of the system when an error occurs in the memory command.

The indirect read of the register works well in proposed DDR4 systems.DDR4 specifies a register device that can perform C/A parity errorchecking, and store offending commands. Thus, in DDR4, the command canbe stopped before execution and the mechanism to access the offendingcommand helps in pinpointing the offending command, which in turn helpsin error recovery.

FIG. 1 is a block diagram of an embodiment of a system having a memorysubsystem with a register accessible via an address bus but not a databus. System 100 represents a computing device or mobile device in whichisolated register 130 is isolated from host processor 110. Hostprocessor 110 executes instructions stored in memory subsystem 120. Hostprocessor 110 generally issues a command to access data. The command caninclude a physical o a virtual address, which points to a specificmemory location within memory devices of memory subsystem 120.

Isolated register 130 is not directly accessed by host processor 110.Register 130 is thus “isolated” from direct access by host processor110, even though it is connected to elements of memory subsystem 120,such as an address bus, which is also connected to a memory controllerand memory devices (see FIGS. 2 and 3 below for more detailed examples).System 100 includes a control mechanism as is known in the art to loaddata and code or instructions into memory subsystem 120 for execution byprocessor 110.

In one embodiment, host processor 110 issues a command that causes datato be stored in register 130, which cannot then be directly accessed byhost processor 110. Examples include Mode Register values, certain debugvalues, parity error information, or other information. In such anembodiment, host processor 110 issues a command that is forwarded toregister 130 to cause the register to copy or transfer its contents to aregister on a memory device of memory subsystem 120. The memory deviceis connected to a data bus, and can thus respond to a command from hostprocessor 110 by loading data onto the data bus, which is readable byhost processor 110.

In one embodiment, BIOS (basic input/output system) 140 includes codethat can be executed by host processor 110 to trigger a read of register130, and process the contents stored in it. For example, host processor110 can be configured to access debug or error correction code stored inBIOS 140 on the occurrence of certain events. Thus, host processor 110can be made to execute a debug state or an error correction state thatwill access the contents of register 130 and determine what actions totake in response to the contents read.

FIG. 2 is a block diagram of an embodiment of a system having a memorysubsystem with a register between a memory controller and a DRAM device.System 200 represents a computing device or mobile device in which aregister is located between memory controller 220 and DRAM 240, and canbe one example of system 100 of FIG. 1. Host processor 210 executesinstructions stored in memory subsystem 202. Host processor 210 canaccess data or code stored in DRAM 240 for execution of instructions. Inone embodiment, memory subsystem 202 includes other memory resources(not shown) in addition to DRAM 240.

Host processor 210 accesses DRAM 240 by generating a command or requestthat it sends to memory controller 220 over host bus 212. Host bus 212represents any connections through which host processor 210 can providea command or request related to memory access. In one embodiment, memorycontroller 220 sends all access requests through register 230, insteadof directly to DRAM 240. In another embodiment (see, for example, FIG. 3below), memory controller can access DRAM 240 directly, and register 230sits on an address bus to which the memory controller and DRAM areconnected.

In one embodiment, address bus 222 and address bus 224 both representthe address bus of memory subsystem 202, where address bus 222 is theaddress bus as between memory controller 220 and register 230, andaddress bus 224 is the address bus as between register 230 and DRAM 240.Register 230 can sit on the address bus between memory controller 220and DRAM 240 to perform an operation on access commands sent by memorycontroller 220 to DRAM 240. In one embodiment, memory controller 220sends all commands to DRAM 240 through register 230. For example, in oneembodiment, register 230 provides parity error checking. In the case ofa detected parity error, register 230 does not forward the offendingcommand. Thus, having register 230 in between memory controller 220 andDRAM 240 can prevent the DRAM operating on a bad command that wouldotherwise cause device 200 to become unresponsive (i.e., hung).

In an implementation where register 230 provides parity error checking,register 230 logs information regarding parity error when it isdetected. When parity error is detected, in addition to stopping thecommand from reaching DRAM 240, register 230 triggers parity error,which is detected by memory controller 220 and/or DRAM 240. Howeverparity error is indicated in system 200, host processor 210 detects theparity error and can attempt to read the contents of register 230 toobtain the parity error log information. The register can then transferits contents to DRAM 240 in response to a read command to enable hostprocessor 210 access to the error log for a determination of how toproceed. Host processor 210 can access the transferred contents ofregister 230, as well as other information stored on DRAM 240, over databus 242. DRAM 240 is connected to data bus 242, whereas register 230 isnot.

FIG. 3 is a block diagram of an embodiment of a system having a memorysubsystem with a register accessible via an address bus but not a databus, and a memory device accessible via both the address bus and databus. System 300 represents a computing device in which host processor310 accesses data indirectly from register 320. System 300 can be oneexample of system 100 of FIG. 1.

Whereas register 230 of FIG. 2 is connected between the memorycontroller and memory device, register 320 is not connected betweenmemory controller 340 and DRAM 330. Instead, register 320 is connectedto memory controller 340 in parallel with DRAM 330 over address bus 302.Register 320 is not connected to data bus 304. DRAM 330 is connected todata bus 304. Memory controller 340 may or may not be connected to databus 304. In one embodiment, memory controller 340 is coupled to hostprocessor 310 via command bus 306, which may or may not be part of databus 304.

Register 320 logs information such as memory configuration values ordebug values. When host processor 310 executes instructions thatindicate reading the value(s) logged in register 320, host processor 310issues a command over command bus 306 to memory controller 340, whichthen provides a command on address bus 302. Host processor 310 is notdirectly connected to address bus 302. Register 320 responds to thecommand by transferring data to DRAM 330 over address bus 302.

In one embodiment, the command for register 320 causes register 320 totransfer to a specific location in DRAM 330. The register specifies thelocation with selection code or selection information. Thus, a readtrigger command can indicate a register of DRAM 330 to which the loginformation should be written. In one embodiment, DRAM 330 includesmultiple memory devices, 332-0, 332-1, . . . , 332-N, where N is aninteger greater than or equal to zero. In one embodiment, each deviceincludes one or more multipurpose registers (MPRs), illustrated indevice 332-0 as MPR[3:0]. There can be more or fewer than four registersin each DRAM device.

In one embodiment, memory controller 340 selects the location to whichregister 320 writes its contents by selecting a location selectionand/or write enable for the desired location in DRAM 330. The readtrigger that causes register 320 to transfer its contents to DRAM 330can include a selection code to indicate a specific MPR. In oneembodiment, the format of the read trigger indicates register 320 as thetransfer source, which is to write into a specified MPR as thedestination. Thus, the read trigger can be a command similar instructure to other standard commands in system 300.

In general, the read trigger causes register 320 to transfer loginformation to a register on DRAM 330, which can then be read by hostprocessor 310. Host processor 310 issues a command that ultimatelycauses read trigger to be sent to register 320. In one embodiment, thecommand from host processor 310 is considered the read trigger, and isforwarded by memory controller 340. In another embodiment, hostprocessor 310 issues a command that causes memory controller to generatea read trigger, which it then sends to register 320.

FIG. 4 is a block diagram of an embodiment of a system having a memorysubsystem with a register device between a memory controller and a DRAMdevice, where the register device performs parity checking. As mentionedabove with respect to the examples of FIGS. 1 and 2, in one embodiment aregister device disposed between the memory controller and the memorydevice can perform parity checking. In system 400, register device 420is located between memory controller 410 and DRAM 430.

Register device 420 includes register 422 where it logs parity checkinginformation. Register 422 is a register in accordance with anyembodiment known in the art. Briefly, a register includes a volatilegroup of digital bits held in a group of circuit elements. In oneembodiment, register device 420 also includes parity check logic 424,which represents hardware and/or software executed on processingresources to perform parity check functions. Parity checking isgenerally a fairly simple logical operation to check that a calculatedparity matches an expected parity, and can be easily implemented insimple digital circuits.

Register device 420 is connected to DRAM 430 via address bus 444. DRAM430 is connected to a host processor via data bus 442. DRAM 430 includesmemory resources 432 that store the data in the DRAM. DRAM 430 alsoincludes one or more MPRs 434, which can function essentially as a smallscratch pad for the DRAM device. In one embodiment, DRAM 430 includesparity check logic 436, which can be implemented in a manner similar toparity check logic 424 of register device 420. In one embodiment, eitheror both of parity check logic 424 and parity check logic 436 areselectively enabled. Thus, parity checking can be enabled or disabled atboth register device 420 and DRAM 430. In one embodiment, when paritychecking is enabled at register device 420, it is disabled at DRAM 430.

Assume for the following description that parity check logic 424 isenabled. If parity check logic 424 detects a parity error, it logsparity error information in register 422, which can be a C/A register.Register device 420 transfers the error log information and error statusinformation to DRAM 430. The same mechanism that register device 420uses to transfer error log information and error status information toDRAM 430 can be used to transfer control words from register device 420.

In one embodiment, register device 420 is on a DIMM (dual inline memorymodule). System 400 sets the bits of register 422 by issuing an addresscommand from memory controller 410. Based on the address, registerdevice 420 sets bits in register 422. As described herein, standardaddress commands can then be used to cause register device 420 totransfer data to MPR 434 to be read over data bus 442. Since registerdevice 420 is isolated from data bus 442, it cannot directly place dataon the data bus for access by a host processor.

In one embodiment, register device 420 is set up to check for a parity(PAR) signal that is generated one clock after a chip select signal(CS#). In an alternate embodiment, the parity signal can be generated inthe same clock cycle as CS#, instead of the clock cycle+1. Registerdevice 420 checks for parity with no errors before forwarding thecommand to DRAM 430. The transfer of the error log from register device420 would work the same whether or not parity check logic 436 is enabledin DRAM 430 (i.e., whether or not the DRAM is checking for parityerrors).

In one embodiment, the process for logging and reading out the loginformation from register device 420 is as follows. The process allowsrecovery from parity error, whereas with traditional approaches a parityerror would cause system failure. Register device 420 detects a parityerror in the command or address. Register 422 logs the errant C/A(column/address) frame (RCW (register control word) location C0 . . .FF). In one embodiment, bits that are logged are C2-C0, ACT_n, BG1-BG0,BA1-BA0, PAR, A17, A16/RAS_n, A15/CAS_n, A14/WE_n, and A13:0, for atotal of 26 bits. Register device 420 sets the parity error status bitto ‘1’ to indicate the parity error in system 400. One significantcontrast from prior parity error checking techniques is that registerdevice 420 can prevent an erroneous instruction from being executed byholding the errant C/A frame, and not forwarding it to DRAM 430.

In one embodiment, register device 420 asserts a signal to memorycontroller 410 to indicate the parity error. The signal could be anALERT_n signal asserted to the memory controller after a delay oftPAR_ALERT_ON_reg for duration of tPAR_ALERT_PW_reg. Register device 420disables parity checking when a parity error is detected, and will onlyresume parity checking after memory controller 410 resets a parity errorstatus bit to ‘0’.

In one embodiment, MPR 434 includes multiple MPR registers, which havedifferent ranks. In one embodiment, MPR Page 0 is a readable andwriteable register, whereas MPR Pages 1, 2, 3 are read-only. Thus,memory controller 410 can enable a ‘MPR Page 0’ mode in DRAM 430 in rank0 by setting MR3 bit A2=1 and A1:A0=00 (page 0). Reads and writes canthus be directed to Page 0.

In one embodiment, memory controller 410 selects the error log registerin an RCW election control word and initiates one or more commands towrite the contents of register 422 to MPR Page 0. In one embodiment,memory controller 410 issues four ‘Send 8-bit RCW to MPR’ commands bywriting to a Command Space control word (address 3F) four times. Such asequence can transfer 32 bits (which may be the entire size of register422) of the error log register to page 0 of MPR0, MPR1, MPR2 and MPR3.Using rank 0 on the DIMM for MPR writes is a convenient when all DIMMshave rank 0. Other ranks could be used instead of rank 0.

In one embodiment, for convenience the mapping of bits to Page 0 canfollow the same pattern as the mapping of bits in Page 1. Page 1 is usedby DRAM for error logs, but may be readable only. If Page 1 isread-only, information can be written to a writeable page (e.g., Page 0)with the same mapping so that the same commands and processing can beused to understand the error information.

In one example embodiment, a write to Page 0 (MPR1) is a writetransaction with BA1:BA0=00 and address A7:A0 mapped as follows:

A[15]/ A[14]/WE# A[13] A[12] A[11] A[10] A[9] A[8] CAS#

After the error log and the error status have been transferred fromregister 422 to DRAM Page0, memory controller 410 can use read commandsto read Page 0. Thus, a host processor can generate read commands tocause the memory controller to use read commands to access the data.

Memory controller 410 can disable MPR operation by programming MR3 A2=0to DRAM, which initiates normal data flow. The memory controller canalso enable parity checking again in register device 420 by resettingthe parity error signal as mentioned above.

In one embodiment, the following register specification details canapply.

TABLE 1 RC3F: Command Space Cmd Command Cmd (DA[3:0]) No Name Result 0 00 0 CMD0 Reserved 0 0 0 1 CMD1 Reserved 0 0 1 0 CMD2 Reserved 0 0 1 1CMD3 Reserved 0 1 0 0 CMD4 Send 8-bit Sends selected RCW RCW to MPRx toDRAM MPR0 page 0. 0 1 0 1 CMD5 Send two 4-bit Sends selected RCWs RCWsto MPRx to DRAM MPR0 page 0. 0 1 1 0 CMD6 Reserved 0 1 1 1 CMD7 Reserved1 0 0 0 CMD8 Reserved 1 0 0 1 CMD9 Reserved 1 0 1 0 CMD10 Reserved 1 0 11 CMD11 Reserved 1 1 0 0 CMD12 Reserved 1 1 0 1 CMD13 Reserved 1 1 1 0CMD14 Reserved 1 1 1 1 CMD15 Reserved

TABLE 2 RC8x: RCW Selection Control Word definition for 8-bit RCWsSetting (DA[7:0]) Definition Encoding 0 MPR MPR A12 A11 A10 A9 A8 RCWaddress for RCW read Selects 1 out of 32 8-bit RCW addresses bit 1 bit 0operation MPR bits[1:0] = 00 selects MPR0 MPR bits[1:0] = 01 selectsMPR1 MPR bits[1:0] = 10 selects MPR2 MPR bits[1:0] = 11 selects MPR3 1MPR MPR A12 A11 A10 A9 A8 RCW address for RCW read Selects 1 out of 328-bit RCW addresses bit 1 bit 0 operation with auto- MPR bits[1:0] = 00selects MPR0 increment^([1]) MPR bits[1:0] = 01 selects MPR1 MPRbits[1:0] = 10 selects MPR2 MPR bits[1:0] = 11 selects MPR3 ^([1])‘Send8-bit RCW to MPRx’ commands auto-increment the address field by 1 andthe MPR bits field in the RCW Selection Control Word by 1.

TABLE 3 RC4x: RCW Selection Control Word definition for 4-bit RCWsSetting (DA[7:0]) Definition Encoding 0 MPR MPR A9 A8 A7 A6 A5 RCWaddress for RCW Selects 1 out of 32 dual 4-bit RCW addresses bit 1 bit 0read operation MPR bits[1:0] = 00 selects MPR0 MPR bits[1:0] = 01selects MPR1 MPR bits[1:0] = 10 selects MPR2 MPR bits[1:0] = 11 selectsMPR3 1 MPR MPR A9 A8 A7 A6 A5 RCW address for RCW Selects 1 out of 32dual 4-bit RCW addresses bit 1 bit 0 read operation with MPR bits[1:0] =00 selects MPR0 auto-increment^([1]) MPR bits[1:0] = 01 selects MPR1 MPRbits[1:0] = 10 selects MPR2 MPR bits[1:0] = 11 selects MPR3 ^([1])‘Sendtwo 4-bit RCWs to MPRx’ commands auto-increment the address field by 1and the MPR bits field in the RCW Selection Control Word by 1.

It will be understood that the register control word (RCW) is part ofthe register device. The DRAM device includes a Mode Register (MR), andthe register device includes the RCW. The RCW and MR have a similarfunction for their two different associated devices. The memorycontroller first selects an RCW to read, and then writes the desiredaddress (the address to read) as the source. The memory controller canthen generate a destination control word to specify the destination (theaddress to write to). Every selected bit in the command space controlword is used to define the command. There may be bits that are reservedor otherwise not used.

To accomplish a write of the register contents, in one embodiment, thememory controller sets the source, sets the destination, and then setsthe Command Space Control Word, which generates and sends out thecontrol word. The system can be configured so that merely setting thesource and destination does not do anything in and of itself.

The RCW Selection Control Word is written prior to a ‘Send 8-bit RCW toMPRx’ or ‘Send two 4-bit RCWs to MPRx’ commands. In one embodiment, theregister device sends the following bits on QxA[7:0] outputs:

TABLE 4 Send RCW to DRAM bit assignment for 4-bit RCWs QxA7 QxA6 QxA5QxA4 QxA3 QxA2 QxA1 QxA0 upper upper upper upper lower lower lower loweraddress address address address address address address address RCW bit3 RCW bit 2 RCW bit 1 RCW bit 0 RCW bit 3 RCW bit 2 RCW bit 1 RCW bit 0

TABLE 5 Send to DRAM bit assignment for 8-bit RCW QxA7 QxA6 QxA5 QxA4QxA3 QxA2 QxA1 QxA0 RCW bit 7 RCW bit 6 RCW bit 5 RCW bit 4 RCW bit 3RCW bit 2 RCW bit 1 RCW bit 0

In one embodiment, the control word locations C0 . . . FF function as a32-bit error log register. In one embodiment, upon occurrence of aparity error, the register device logs the following sampled command andaddress bits in the Error Log Register, which can be transferred by thememory controller to page 0 of the DRAM MPR, where it can be read by thehost system (via the processor).

TABLE 6 RCC0 . . . RCFF: Error Log Register Control Word Setting(DA[7:0]) RCCx A7 A6 A5 A4 A3 A2 A1 A0 RCDx A17/CAS_n A14/WE_n A13 A12A11 A10 A9 A8 RCEx DPAR ACT_n BG1 BG0 BA1 BA0 A17 A16/RAS_n RCFxReserved CA Parity Error Status^([1]) Reserved C2 C1 C0 ^([1])Theregister device sets this bit upon occurrence of a CA parity error.Writing this bit to ‘0’ resumes parity checking. While this bit is setand the device is in either one of the two cycle N + 1 parity modes, thedevice will not assert any of its QxCSy_n outputs.

In one embodiment, the indirect read of a register device as describedherein is applied to DDR4, which can be implemented with parity checkingin a register device as described above. In more particular detail withrespect to DDR4 MPR Mode, one embodiment of DDR4 DRAM contains fourpages of MPR registers, and each page has four MPR locations. Page 0 hasfour 8 bit programmable MPR locations used for DQ bit pattern storage.These MPR registers are written by first placing the DRAM in ‘Dataflowfrom/to MPR’ mode by setting a mode register A2=1 in MR3. The MPR pageis also set using bits A1:A0 in MR3.

In this mode, an MRS (mode register set) command is used to program theMPRs. For an MRS command, the address bus is used for the data. Onceprogrammed, the registers can be accessed with read commands in ‘MPRoperation’ mode to drive the MPR bits onto the DQ bus to the memorycontroller or host.

DDR4 MPR mode enable and page selection are accomplished by a ModeRegister command as shown below.

TABLE 7 MR3 Address Operating Mode Description A2 MPR operation 0 =Normal 1 = Dataflow from/to MPR A1:A0 MPR Selection 00 = page0 01 =page1 10 = page2 11 = page3

As mentioned above, four MPR pages are provided in DDR4 SDRAM. Page 0 isfor both read and write, and pages 1, 2, and 3 are read-only. Any MPRlocation (MPR0-3) in page 0 can be readable through any of three readoutmodes (serial, parallel, or staggered), but pages 1, 2, and 3 supportonly the serial readout mode.

After power up, the content of the MPR page 0 should have default valuesas predefined for the DRAM device. MPR page 0 can be writeable only whenan MPR write command is issued by the memory controller. Unless an MPRwrite command is issued, the DRAM must keep the default valuespermanently, and should not change the content on its own for anypurpose.

TABLE 8 MPR Default Values MPR Address Location [7] [6] [5] [4] [3] [2][1] [0] NOTE BA1:BA0 00 = MPR0 0 1 0 1 0 1 0 1 Read/ 01 = MPR1 0 0 1 1 00 1 1 Write 10 = MPR2 0 0 0 0 1 1 1 1 (Default 11 = MPR3 0 0 0 0 0 0 0 0Value)

It will be understood that reference, even detailed reference asprovided above, with respect to DDR4 and DDR4 parity error checking, ismerely a non-limiting example. As described herein, the indirect-readmechanism of the register can function for all registers that areisolated from a data bus, but coupled to a device that is coupled to thedata bus.

FIG. 5 is a flow diagram of an embodiment of a process for accessingdata from a register accessible via an address bus but not a data bus.In one embodiment, a memory controller sends a command to a registerdevice that triggers the register device to store or log information ina register, 502. The information can be parity error information, debuginformation, configuration information, or other information that can bestored in a register isolated from the system data bus.

In one embodiment, the information to store in the register isconfiguration information, and the trigger is a command from the memorycontroller to write the configuration information. In one embodiment,the information to store is parity error information, and the trigger isdetection by the register device that a parity error has occurred. Inone embodiment, the information to store is debug information, and thetrigger is a command from the memory controller in response to the debugsoftware to write data to the register. In response to the trigger, theregister device logs the information in the register, 504.

The memory controller detects a read trigger to read the informationstored in the register, 506. The memory controller generally receivessuch a trigger from a process executed by the host processor. Theprocess can be a program executing on the host, or it can be code storedin the device BIOS. In one embodiment, the memory controller preparesfor reading the register by identifying a source and destination inresponse to the read trigger, 508. In one embodiment, the read triggeris a command that is of a form that identifies a specific registerlocation as the source, and a specific MPR location of the memory deviceas the destination. The memory controller can prepare the command to theregister device and DRAM identifying the specific locations based on theidentification of the information to be read by the host.

In response to the command from the memory controller, the registerdevice writes its contents (the source) to the MPR location specified(the destination), 510. The host can then read the information from thedestination in the memory device with standard read commands over thesystem data bus, 512. The host that requested the information determinesone or more actions based on the information read, 514. The actions canbe related to setting or updating configuration, storing data in storageor sending data over a network, identifying a command with parity errorand issuing a corrected command, or any other action.

In one embodiment, a BIOS controls at least certain command to theregister device. For example, in response to a parity error, the BIOScan see that an error occurred, and then go back to the host to discoverthe specific error. The specific error is visible by reading theregister device as set forth above. In one embodiment, in response to anerror, the BIOS can attempt to read every device register in the systemto figure out where the error came from, and what specifically the erroris. The software controls the writing and reading of the registers andthe commands. The BIOS then determines what actions to take based on thespecific error.

FIG. 6 is a block diagram of an embodiment of a computing system inwhich a register of the memory subsystem is accessed indirectly by ahost processor. System 600 represents a computing device in accordancewith any embodiment described herein, and can be a laptop computer, adesktop computer, a server, a gaming or entertainment control system, ascanner, copier, printer, or other electronic device. System 600includes processor 620, which provides processing, operation management,and execution of instructions for system 600. Processor 620 can includeany type of microprocessor, central processing unit (CPU), processingcore, or other processing hardware to provide processing for system 600.Processor 620 controls the overall operation of system 600, and can beor include, one or more programmable general-purpose or special-purposemicroprocessors, digital signal processors (DSPs), programmablecontrollers, application specific integrated circuits (ASICs),programmable logic devices (PLDs), or the like, or a combination of suchdevices.

Memory subsystem 630 represents the main memory of system 600, andprovides temporary storage for code to be executed by processor 620, ordata values to be used in executing a routine. Memory subsystem 630includes memory 632, which represents one or more memory devices thatcan include read-only memory (ROM), flash memory, one or more varietiesof random access memory (RAM), or other memory devices, or a combinationof such devices. In one embodiment, memory 632 includes at least oneDRAM device. Memory subsystem 630 includes register 634, whichrepresents a register that is not directly readable by processor 620.Such a register can be referred to as an isolated register, and can beread indirectly as described herein.

Memory subsystem 630 stores and hosts, among other things, operatingsystem (OS) 636 to provide a software platform for execution ofinstructions in system 600. Additionally, other instructions 638 arestored and executed from memory subsystem 630 to provide the logic andthe processing of system 600. OS 636 and instructions 638 are executedby processor 620.

Processor 620 and memory subsystem 630 are coupled to bus/bus system610. Bus 610 is an abstraction that represents any one or more separatephysical buses, communication lines/interfaces, and/or point-to-pointconnections, connected by appropriate bridges, adapters, and/orcontrollers. Therefore, bus 610 can include, for example, one or more ofa system bus, a Peripheral Component Interconnect (PCI) bus, aHyperTransport or industry standard architecture (ISA) bus, a smallcomputer system interface (SCSI) bus, a universal serial bus (USB), oran Institute of Electrical and Electronics Engineers (IEEE) standard1394 bus (commonly referred to as “Firewire”). The buses of bus 610 canalso correspond to interfaces in network interface 650.

In one embodiment, bus 610 includes a data bus that is a data busincluded in memory subsystem 630 over which processor 630 can readvalues from memory 632. The additional line shown linking processor 620to memory subsystem 630 represents a command bus over which processor620 provides commands and addresses to access memory 632. Register 634is connected to a data bus of memory subsystem 630, but not to the databus of bus 610.

System 600 also includes one or more input/output (I/O) interface(s)640, network interface 650, one or more internal mass storage device(s)660, and peripheral interface 670 coupled to bus 610. I/O interface 640can include one or more interface components through which a userinteracts with system 600 (e.g., video, audio, and/or alphanumericinterfacing). Network interface 650 provides system 600 the ability tocommunicate with remote devices (e.g., servers, other computing devices)over one or more networks. Network interface 650 can include an Ethernetadapter, wireless interconnection components, USB (universal serialbus), or other wired or wireless standards-based or proprietaryinterfaces.

Storage 660 can be or include any conventional medium for storing largeamounts of data in a nonvolatile manner, such as one or more magnetic,solid state, or optical based disks, or a combination. Storage 660 holdscode or instructions and data 662 in a persistent state (i.e., the valueis retained despite interruption of power to system 600). Storage 660can be generically considered to be a “memory,” although memory 630 isthe executing or operating memory to provide instructions to processor620. Whereas storage 660 is nonvolatile, memory 632 can include volatilememory (i.e., the value or state of the data is indeterminate if poweris interrupted to system 600).

Peripheral interface 670 can include any hardware interface notspecifically mentioned above. Peripherals refer generally to devicesthat connect dependently to system 600. A dependent connection is onewhere system 600 provides the software and/or hardware platform on whichoperation executes, and with which a user interacts.

FIG. 7 is a block diagram of an embodiment of a mobile device in which aregister of the memory subsystem is accessed indirectly by a hostprocessor. Device 700 represents a mobile computing device, such as acomputing tablet, a mobile phone or smartphone, a wireless-enablede-reader, or other mobile device. It will be understood that certain ofthe components are shown generally, and not all components of such adevice are shown in device 700.

Device 700 includes processor 710, which performs the primary processingoperations of device 700. Processor 710 can include one or more physicaldevices, such as microprocessors, application processors,microcontrollers, programmable logic devices, or other processing means.The processing operations performed by processor 710 include theexecution of an operating platform or operating system on whichapplications and/or device functions are executed. The processingoperations include operations related to I/O (input/output) with a humanuser or with other devices, operations related to power management,and/or operations related to connecting device 700 to another device.The processing operations can also include operations related to audioI/O and/or display I/O.

In one embodiment, device 700 includes audio subsystem 720, whichrepresents hardware (e.g., audio hardware and audio circuits) andsoftware (e.g., drivers, codecs) components associated with providingaudio functions to the computing device. Audio functions can includespeaker and/or headphone output, as well as microphone input. Devicesfor such functions can be integrated into device 700, or connected todevice 700. In one embodiment, a user interacts with device 700 byproviding audio commands that are received and processed by processor710.

Display subsystem 730 represents hardware (e.g., display devices) andsoftware (e.g., drivers) components that provide a visual and/or tactiledisplay for a user to interact with the computing device. Displaysubsystem 730 includes display interface 732, which includes theparticular screen or hardware device used to provide a display to auser. In one embodiment, display interface 732 includes logic separatefrom processor 710 to perform at least some processing related to thedisplay. In one embodiment, display subsystem 730 includes a touchscreendevice that provides both output and input to a user.

I/O controller 740 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 740 can operate tomanage hardware that is part of audio subsystem 720 and/or displaysubsystem 730. Additionally, I/O controller 740 illustrates a connectionpoint for additional devices that connect to device 700 through which auser might interact with the system. For example, devices that can beattached to device 700 might include microphone devices, speaker orstereo systems, video systems or other display device, keyboard orkeypad devices, or other I/O devices for use with specific applicationssuch as card readers or other devices.

As mentioned above, I/O controller 740 can interact with audio subsystem720 and/or display subsystem 730. For example, input through amicrophone or other audio device can provide input or commands for oneor more applications or functions of device 700. Additionally, audiooutput can be provided instead of or in addition to display output. Inanother example, if display subsystem includes a touchscreen, thedisplay device also acts as an input device, which can be at leastpartially managed by I/O controller 740. There can also be additionalbuttons or switches on device 700 to provide I/O functions managed byI/O controller 740.

In one embodiment, I/O controller 740 manages devices such asaccelerometers, cameras, light sensors or other environmental sensors,gyroscopes, global positioning system (GPS), or other hardware that canbe included in device 700. The input can be part of direct userinteraction, as well as providing environmental input to the system toinfluence its operations (such as filtering for noise, adjustingdisplays for brightness detection, applying a flash for a camera, orother features).

In one embodiment, device 700 includes power management 750 that managesbattery power usage, charging of the battery, and features related topower saving operation. Memory subsystem 760 includes memory devices forstoring information in device 700. Memory can include nonvolatile (statedoes not change if power to the memory device is interrupted) and/orvolatile (state is indeterminate if power to the memory device isinterrupted) memory devices. Memory resources of memory subsystem 760can store application data, user data, music, photos, documents, orother data, as well as system data (whether long-term or temporary)related to the execution of the applications and functions of system700.

In one embodiment, at least one memory device 762 includes a registerdirectly accessible by processor 710. Register device 764 of memorysubsystem 760 is outside memory devices 762, and is not directlyaccessible by processor 710, but is communicatively coupled to memorydevice 762 via an address bus, as described above. Data stored inregister device 764 can be transferred to the register of memory device762 to be read by processor 710.

Connectivity 770 includes hardware devices (e.g., wireless and/or wiredconnectors and communication hardware) and software components (e.g.,drivers, protocol stacks) to enable device 700 to communicate withexternal devices. The device could be separate devices, such as othercomputing devices, wireless access points or base stations, as well asperipherals such as headsets, printers, or other devices.

Connectivity 770 can include multiple different types of connectivity.To generalize, device 700 is illustrated with cellular connectivity 772and wireless connectivity 774. Cellular connectivity 772 refersgenerally to cellular network connectivity provided by wirelesscarriers, such as provided via GSM (global system for mobilecommunications) or variations or derivatives, CDMA (code divisionmultiple access) or variations or derivatives, TDM (time divisionmultiplexing) or variations or derivatives, or other cellular servicestandards. Wireless connectivity 774 refers to wireless connectivitythat is not cellular, and can include personal area networks (such asBluetooth), local area networks (such as WiFi), and/or wide areanetworks (such as WiMax), or other wireless communication. Wirelesscommunication refers to transfer of data through the use of modulatedelectromagnetic radiation through a non-solid medium. Wiredcommunication occurs through a solid communication medium.

Peripheral connections 780 include hardware interfaces and connectors,as well as software components (e.g., drivers, protocol stacks) to makeperipheral connections. It will be understood that device 700 could bothbe a peripheral device (“to” 782) to other computing devices, as well ashave peripheral devices (“from” 784) connected to it. Device 700commonly has a “docking” connector to connect to other computing devicesfor purposes such as managing (e.g., downloading and/or uploading,changing, synchronizing) content on device 700. Additionally, a dockingconnector can allow device 700 to connect to certain peripherals thatallow device 700 to control content output, for example, to audiovisualor other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, device 700 can make peripheral connections 780 viacommon or standards-based connectors. Common types can include aUniversal Serial Bus (USB) connector (which can include any of a numberof different hardware interfaces). DisplayPort including MiniDisplayPort(MDP), High Definition Multimedia Interface (HDMI), Firewire, or othertype.

Flow diagrams as illustrated herein provide examples of sequences ofvarious process actions. Although shown in a particular sequence ororder, unless otherwise specified, the order of the actions can bemodified. Thus, the illustrated embodiments should be understood only asan example, and the process can be performed in a different order, andsome actions can be performed in parallel. Additionally, one or moreactions can be omitted in various embodiments; thus, not all actions arerequired in every embodiment. Other process flows are possible.

To the extent various operations or functions are described herein, theycan be described or defined as software code, instructions,configuration, and/or data. The content can be directly executable(“object” or “executable” form), source code, or difference code(“delta” or “patch” code). The software content of the embodimentsdescribed herein can be provided via an article of manufacture with thecontent stored thereon, or via a method of operating a communicationinterface to send data via the communication interface. A machinereadable storage medium can cause a machine to perform the functions oroperations described, and includes any mechanism that stores informationin a form accessible by a machine (e.g., computing device, electronicsystem, etc.), such as recordable/non-recordable media (e.g., read onlymemory (ROM), random access memory (RAM), magnetic disk storage media,optical storage media, flash memory devices, etc.). A communicationinterface includes any mechanism that interfaces to any of a hardwired,wireless, optical, etc., medium to communicate to another device, suchas a memory bus interface, a processor bus interface, an Internetconnection, a disk controller, etc. The communication interface can beconfigured by providing configuration parameters and/or sending signalsto prepare the communication interface to provide a data signaldescribing the software content. The communication interface can beaccessed via one or more commands or signals sent to the communicationinterface.

Various components described herein can be a means for performing theoperations or functions described. Each component described hereinincludes software, hardware, or a combination of these. The componentscan be implemented as software modules, hardware modules,special-purpose hardware (e.g., application specific hardware,application specific integrated circuits (ASICs), digital signalprocessors (DSPs), etc.), embedded controllers, hardwired circuitry,etc.

Besides what is described herein, various modifications can be made tothe disclosed embodiments and implementations of the invention withoutdeparting from their scope. Therefore, the illustrations and examplesherein should be construed in an illustrative, and not a restrictivesense. The scope of the invention should be measured solely by referenceto the claims that follow.

What is claimed is:
 1. An apparatus comprising: a dynamic random accessmemory (DRAM) comprising at least one page having at least onemultipurpose register (MPR) and comprising: a first interface that, whenoperatively coupled to an address bus, is to receive a control word (CW)and provide the CW to a particular MPR and a second interfacecommunicatively coupled to the at least one page having at least oneMPR, wherein: the at least one page having at least one MPR to bewritten-to using the first interface during a coupling of the firstinterface to the address bus and to be read-from using the secondinterface during a coupling of the second interface to a data bus. 2.The apparatus of claim 1, wherein the CW comprises a 4-bit CW or an8-bit CW.
 3. The apparatus of claim 1, wherein the particular MPRcomprises an MPR number zero (MPR0) of page 0 and the CW is associatedwith a command CMD4.
 4. The apparatus of claim 1, wherein: the CW isassociated with a read operation, the read operation is associated withan 8-bit value having positions [7:0] and having at least an MPR bit 1in position 6 and an MPR bit 0 in position 5, and a combination of MPRbit 1 and bit 0 to select a particular MPR number.
 5. The apparatus ofclaim 1, wherein: the CW is associated with a read operation withauto-increment of an address field, the read operation withauto-increment of an address field is associated with an 8-bit valuehaving positions [7:0] and having at least an MPR bit 1 in position 6and an MPR bit 0 in position 5, and a combination of MPR bit 1 and bit 0to select a particular MPR number.
 6. The apparatus of claim 1, furthercomprising: an address bus communicatively coupled to the firstinterface; a register communicatively coupled to the address bus; and amemory controller communicatively coupled to the register, the memorycontroller to provide the CW to the register, select a page and MPRwithin the selected page to receive the CW, and provide one or morecommands to cause writing of the CW to the selected page and MPR.
 7. Theapparatus of claim 6, further comprising: a data bus communicativelycoupled to the second interface and a processor communicatively coupledto the data bus, wherein: the data bus interface is to provide contentfrom an MPR to the processor via the data bus.
 8. The apparatus of claim6, wherein the register is to perform parity checking.
 9. Acomputer-implemented method comprising: receiving, at a multipurposeregister (MPR), a control word (CW) from an address bus interface,wherein the MPR is associated with a dynamic random access memory (DRAM)and wherein the CW is received during a coupling of the address businterface with an address bus, and transmitting content from the MPRusing a data bus interface during a coupling of the data bus interfacewith a data bus.
 10. The method of claim 9, wherein the CW comprises a4-bit CW or an 8-bit CW.
 11. The method of claim 9, wherein the MPRcomprises an MPR number zero (MPR0) of a page 0 and the CW is associatedwith a command CMD4.
 12. The method of claim 9, wherein: the CW isassociated with a read operation, the read operation is associated withan 8-bit value having positions [7:0] and having at least an MPR bit 1in position 6 and an MPR bit 0 in position 5, and a combination of MPRbit 1 and bit 0 to select a particular MPR number.
 13. The method ofclaim 9, wherein: the CW is associated with a read operation withauto-increment of an address field, the read operation withauto-increment of an address field is associated with an 8-bit valuehaving positions [7:0] and having at least an MPR bit 1 in position 6and an MPR bit 0 in position 5, and a combination of MPR bit 1 and bit 0to select a particular MPR number.
 14. An apparatus to write a controlword (CW), the apparatus comprising: a register; a memory controller toprovide a command, the command to cause the register to write a CW to atleast, one multipurpose register (MPR) associated with a dynamic randomaccess memory (DRAM); and an address bus interface communicativelycoupled to the register, the address bus interface to provide the CW fortransfer to an MPR associated with, the command.
 15. The apparatus ofclaim 14, wherein the command comprises a command CMD4 to send a CW toMPR0 of page 0 and the MPR0 of page 0 is to receive the CW from anaddress bus.
 16. The apparatus of claim 14, wherein: the CW isassociated with a read operation, the read operation is associated withan 8-bit value having positions [7:0], and having at least an MPR bit 1in position 6 and an MPR bit 0 in position 5, and a combination of MPRbit 1 and bit 0 to select a particular MPR number.
 17. The apparatus ofclaim 14, wherein: the CW is associated with a read operation withauto-increment of an address field, the read operation withauto-increment of an address field is associated with an 8-bit valuehaving positions [7:0] and having at least an MPR bit 1 in position 6and an MPR bit 0 in position 5, and a combination of MPR bit 1 and bit 0to select a particular MPR number.
 18. The apparatus of claim 14,wherein the memory controller comprises any or a combination of:software executed by one or more processors, hardware, or firmware. 19.The apparatus of claim 14, further comprising: a memory devicecomprising the DRAM, the DRAM comprising at least one page having atleast one MPR; an address bus communicatively coupled to the address businterface and to the memory device; a data bus communicatively coupledto the at least one MPR; and a processor communicatively coupled to thedata bus, wherein the MPR is to provide content to the processor via thedata bus.
 20. The apparatus of claim 19, further comprising: a physicallayer logic; a radio communicatively coupled to the physical layerlogic; at least one antenna communicatively coupled to the radio; and adisplay communicatively coupled to the processor.